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Nios Ⅱ处理器是Altera公司推出的基于SOPC系统的嵌入式软核处理器。在Quartus Ⅱ软件的SOPC Builder工具中,用户可以利用Nios Ⅱ处理器、标准配套外围设备以及用户自定义的逻辑接口IP核来创建适用的Nios Ⅱ嵌入式系统,再将设计下载到Altera公司的FPGA中进行实现。本文在Quartus Ⅱ软件中使用Verilog硬件描述语言创建了基于Avalon总线的ISA总线接口逻辑,并在SOPC Builder中实现对此元件的封装,使之成为可供Nios Ⅱ系统使用IP核。
Nios Ⅱ processor is Altera’s SOPC system based on the embedded soft-core processor. In the Quartus Ⅱ software SOPC Builder tool, users can use Nios Ⅱ processor, standard peripherals and user-defined logic interface IP core to create a suitable Nios Ⅱ embedded system, and then download the design to Altera’s FPGA In the realization. This article uses Verilog hardware description language to create ISA bus interface logic based on Avalon bus in Quartus II software, and encapsulates this component in SOPC Builder, making it possible for Nios II system to use IP core.