This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 μm CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2. This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 μm CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm 2.