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众所周知,计算机的加法器可以由一个完全独立的加法器,用一个由某一模数余数来表示的校验符号来进行校验。本文叙述这种剩余数校验系统,并且还证明了,单独加法及校验线路只有采用这种校验系统才有可能。本文还讨论了当发生溢出时处理剩余校验符号的方法。
It is well-known that a computer adder can be verified by a completely separate adder using a check symbol represented by a modular remainder. This paper describes this residual number verification system and also proves that it is only possible to use this verification system with separate addition and verify lines. This article also discusses ways to handle the remaining check symbols when an overflow occurs.