流水线技术是FPGA设计速度优化的有效方法之一。通过不同流水线级数和不同位宽的加法器和乘法器综合数据的对比,说明在用FPGA实现数字信号处理硬件化运算中流水线技术的有效性和选择方法。对流水线应用中设计方法的选择、流水线首次延时和寄存器触发时间、嵌入式存储器块的使用、控制流水线和数据流水线的划分等需要注意的关键问题进行了简要分析。 Pipelining is one of the most effective ways to optimize FPGA design speed. Through the comparison of the integrated data of adder and multiplier with different pipeline stages and different bit widths, the effectiveness and selection method of pipeline technology in the hardware operation of digital signal processing using FPGA are described. The key problems that should be noticed, such as the choice of design method in pipeline application, the first delay in pipeline and register triggering time, the use of embedded memory block, the division of control pipeline and data pipeline, are analyzed briefly.