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在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。
Based on a fully differential folded cascode-shared-source operational amplifier, a BiCMOS sample-and-hold circuit is designed. The circuit uses an input bootstrap switch to improve linearity while designing a high-speed, high-precision op amp that has a settling time of only 1.37 ns and improves circuit speed and accuracy. The dual-channel common-mode feedback circuit in the designed op amp stabilizes the common-mode voltage for about 1.5 ns. The simulation results of SMIC’s 0.25μm BiCMOS process parameters in Cadence Specter show that when the input sinusoidal voltage frequency fI is 10 MHz, the peak-to-peak UP-P is 1 V and the supply voltage VDD is 3 V, The designed spurious-free dynamic range SFDR of the sample / hold circuit is about -61 dB at a sampling frequency of fS of 250 MHz, the signal-to-noise ratio is about 62 dB, and the total circuit power dissipation PD is about 10.85 mW, 10-bit low-voltage, high-speed A / D converter design.