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有限冲击响应(FIR)滤波器是数字通信系统中常用的基本模块。文章设计了一种流水结构的FIR滤波器,通过FPGA对其进行硬件加速控制。仿真结果验证了所设计的FIR流水结构滤波器功能的正确性。
Finite impulse response (FIR) filters are common basic modules in digital communication systems. The article designed a water structure FIR filter, FPGA hardware acceleration control. The simulation results verify the correctness of the FIR filter structure.