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提出了一种无存储访问冲突的基2×K并行FFT架构.该架构通过并行地址产生算法,使K个基2蝶形运算单元同时读取或写入所需的2 K个操作数,达到平均每周期完成K个基2蝶式运算的处理能力.与已有的并行FFT架构相比,新架构地址产生电路简单,并且对于不同的K值,并行地址产生模块结构相同.在资源消耗方面,不考虑旋转因子,N点FFT处理器只需要3 N/2个存储单元.
A non-memory access conflict based 2 × K parallel FFT architecture is proposed in this paper. By using parallel address generation algorithm, K 2 radix-2 butterfly units simultaneously read or write the required 2 K operands to The average per cycle to complete the basis of two K-2 butterfly operations.Compared with the existing parallel FFT architecture, the new architecture address generation circuit is simple, and for different values of K, the parallel address generation module structure is the same in terms of resource consumption , Regardless of the twiddle factor, the N-point FFT processor requires only 3 N / 2 memory cells.