基于0.18μm CMOS工艺,采用离散3阶前馈结构,设计了一种低功耗音频调制器。采用4位SAR量化器,相比于Flash ADC类型的量化器,减少了比较器的个数,降低了量化器的功耗。与传统的利用有源加法器对输入信号和积分器输出进行求和的方式不同,该设计利用SAR量化器实现输入信号的求和,极大地降低了整个调制器的功耗。此外,调制器采用增益提高型低功耗放大器结构,相比于套筒式共源共栅放大器、折叠式共源共栅放大器等传统类型的放大器,节省了功耗。仿真结果表明,在20kHz信号带宽、1.8V电源电压下,调制器的SNDR为94.6dB,SFDR为107dB,功耗仅为145μW。 Based on the 0.18μm CMOS process, a discrete 3-order feedforward architecture is adopted to design a low-power audio modulator. The 4-bit SAR quantizer, compared to the Flash ADC type quantizer, reduces the number of comparators and reduces the quantizer power consumption. Different from the traditional method of summing the input signal and integrator output by active adders, the design uses the SAR quantizer to sum up the input signals and greatly reduces the power consumption of the entire modulator. In addition, the modulator features a gain-enhanced, low-power amplifier architecture that consumes less power than conventional amplifiers such as sleeve-type cascode amplifiers, folded cascode amplifiers and the like. The simulation results show that the modulator has an SNDR of 94.6dB, a SFDR of 107dB and a power consumption of only 145μW at a signal bandwidth of 20kHz and a supply voltage of 1.8V.