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A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs’ skews by adjusting the boosted voltage.A similar bridged capacitors’ charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch’s demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.
A sampling switch with an embedded digital-to-skew converter (DSC) is presented. The proposed switch eliminates time-interleaved ADCs ’skews by adjusting the boosted voltage. A similar bridged capacitors’ charge sharing structure is used to minimize the area. The circuit is fabricated in a 0.18 μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS / s. The power consumption is 430 μW at maximum. The measurement result also includes a 2-channel 14-bit 100 MS / s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch’s demonstration. This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.