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高速数字电路中的信号完整性问题本质上是一个复杂的电磁场问题,人工计算难以对其进行定量分析。Cadence相比于其它EDA工具,可针对高速数字电路设计的不同阶段进行仿真,并根据仿真结果对PCB设计进行条件约束。本文依据仿真结果,通过调整层叠结构、优化匹配电阻、约束线间距及耦合长度等措施,提高PCB信号质量。电路PCB布线完成后,对关键信号进行仿真,验证布局、布线的可靠性。
The problem of signal integrity in high-speed digital circuits is essentially a complex electromagnetic problem that is difficult to quantify by manual calculations. Compared to other EDA tools, Cadence simulates different stages of high-speed digital circuit design and conditions the PCB design based on the simulation results. Based on the simulation results, this paper improves the PCB signal quality by adjusting the laminated structure, optimizing the matching resistance, spacing and length of confinement lines. Circuit PCB layout is completed, the key signal simulation to verify the layout, wiring reliability.