序言自从集成注入逻辑(I~2L)[1]和并合三极管逻辑(MTL)[2]对双极型集成电路产生巨大影响以来,围绕着进一步提高器件的密度和速度展开了大量的研究工作。用标准的隐埋收集极工艺(SBC)生产的 I~2L 表明,每个反相器的最小延迟时间在20ns 左右。为了减小这个比较大的传输延迟可以采用离了注入[3],肖特基二极管和氧化隔离等更先进的生产工艺。下面将讨论用氧化隔离来实现具有更高组装密度和速度的 I~2L 电路。由于它的生产工艺 Preamble Since the integrated logic (I ~ 2L) [1] and the combined transistor logic (MTL) [2] have had a tremendous impact on bipolar integrated circuits, much research has been devoted to further increasing the density and speed of devices . I ~ 2L produced with a standard buried collector process (SBC) shows that the minimum delay time per inverter is around 20 ns. In order to reduce this relatively large transmission delay, more advanced manufacturing processes such as injection [3], Schottky diodes, and oxide isolation can be used. I ~ 2L circuits with higher packing density and speed will be discussed below with oxide isolation. Because of its production process