在当前的国际集成电路市场上,有近50%的芯片属于专用集成电路.专用集成电路的要求是设计周期短,成本低,品种多,批量小.门阵列技术是一种适合专用集成电路设计要求的母片式设计方法,其逻辑功能用已有的库单元进行组合,因而具有较高的可靠性和短的设计周期. 复旦大学微电子所CAD研究室开发的门阵列版图设计系统GALS完成从逻辑图输入到版图的自动设计过程,并且具有电路分析和版图提取验证的功能.该系统采用硅栅CMOS工艺,针对单层金属布线模式. In the current international IC market, nearly 50% of the chips belong to ASICs, which are characterized by short design cycle, low cost, variety and small batch size.Gate array technology is a suitable ASIC design Requirements of the mother-chip design method, the logical function of the existing library unit combination, which has high reliability and short design cycle. Fudan University Institute of Microelectronics CAD developed the gate array layout design system GALS completed From logic input to layout automatic design process, and has the circuit analysis and layout extraction verification function.The system uses silicon gate CMOS technology, for single-layer metal wiring mode.