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针对聚芯SoC的结构特点,提出了一种适用于聚芯SoC的面向低功耗的可重构技术。概述了可重构技术的相关研究,提出了针对聚芯SoC中片上cache的可重构技术,并详细叙述了软硬件两种实现方法,给出了与传统方法功耗比较的实验结果。实验表明,对于Qsort程序,该方法相对传统方法可以降低35.3%的功耗,对于D ijkstra程序,该方法相对传统方法也可以降低46%的功耗。
Aiming at the structural characteristics of poly-core SoCs, a low-power reconfigurable technology for poly-core SoCs is proposed. The researches on reconfigurable technology are summarized. A reconfigurable technology for on-chip cache in SoC is proposed. Two hardware and software implementations are described in detail, and the experimental results of power consumption comparison with traditional methods are given. Experiments show that this method can reduce the power consumption by 35.3% compared with the traditional method for the Qsort program, and reduce the power consumption by 46% compared with the traditional method for the Dijkstra program.