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A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.
A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage , two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ / conv step.