文章根据核心网路由器的高速设计要求,从节约FPGA资源的角度出发,提出了一种高速报文分合路单元的设计实现方法,在FPGA资源和报文处理速度之间找到了一个平衡点,利用有限的FPGA资源达到了10Gbps的线速转发指标,有效的解决了资源与速度互换的矛盾。 According to the high-speed design requirements of core network routers, aiming at saving FPGA resources, this paper proposes a design and implementation method of high-speed packet switch units, finding a balance point between FPGA resources and packet processing speed. The use of limited FPGA resources to achieve 10Gbps wire-speed forwarding indicators, effectively solve the contradiction between resources and speed swap.