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为了进一步减小电容阵列DAC占用的面积,提出了一种可用于SAR ADCs的二分电容阵列(三段电容阵列,T-SC)结构。与传统二段电容阵列相比,提出的二分电容阵列在不增加对电容匹配性要求的前提下,减少了芯片面积。在理论上分析了该结构的电容失配和寄生效应,归纳提出了一种计算电容阵列DAC DNL的简易公式。Matlab仿真结果与理论分析有较好的一致性,三段电容阵列结构能够实现较好的二进制权重特性;根据提出的计算DNL的简易公式进行参数设计,仿真DNL标准偏差为0.51LSB,与理论计算0.5LSB相差0.01LSB。
In order to further reduce the area occupied by the capacitor array DAC, a two-capacitor array (three-segment capacitor array, T-SC) structure that can be used for SAR ADCs is proposed. Compared with the traditional two-segment capacitor array, the proposed two-point capacitor array reduces the chip area without increasing the requirement for capacitance matching. In theory, the structure mismatch and parasitics are analyzed. A simple formula to calculate the capacitance DNL of a capacitor array is given. Matlab simulation results are in good agreement with the theoretical analysis. The three-segment capacitor array structure can achieve better binary weight characteristics. According to the proposed simple formula for calculating DNL parameters, the standard deviation of DNL simulation is 0.51LSB. Compared with the theoretical calculation 0.5LSB difference 0.01LSB.