本文利用时钟信号的竞争冒险现象 ,提出了CMOS时钟信号竞争型三值D型边沿触发器的逻辑设计 .通过PSPICE程序模拟 ,证实了该设计具有正确的逻辑功能 ,而且与传统的三值D型维持阻塞触发器相比 ,它具有更简单的结构和更低的功耗 . In this paper, the logic design of CMOS clock signal competing ternary D-type flip-flop is proposed by using the competition phenomenon of clock signal.The PSPICE program simulation proves that the design has the correct logic function and is compatible with the traditional ternary D-type It maintains a simpler structure and consumes less power than maintaining a blocking flip-flop.