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Futurebus(?)是IEEE资助开发的90年代和下一世纪使用的新型总线,它是结合大多数总线的最优性能的一种强适应性的底板总线,采用了总线底板收发器逻辑(BTL)技术,具有支持高速缓冲存取的功能,适用于通用多处理器系统,可以连接不同性能,不同技术水平的设备,本文介绍了Futurebus~+的特性及主要构成,并分析了该总线所采用的总线底板收发器逻辑(BTL)技术以及提高性能的技术措施,还介绍了一些为Futurebus~+总线标准开发的专用芯片.
The Futurebus (?), A new bus used by the IEEE-funded development of the 90’s and the next century, is a highly adaptable backplane bus that combines optimal performance with most buses using the Bus Backplane Transceiver Logic (BTL) Technology, has the function that supports the cache access, is suitable for the general multiprocessor system, can connect the apparatus of different performance, different skill levels, this text introduced Futurebus ~ + characteristic and main structure, and analyzed this bus line adopted Bus Backplane Transceiver Logic (BTL) technology and technical measures to improve performance, and also introduced some dedicated chips developed for the Futurebus ~ + bus standard.