Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

来源 :电路与系统(英文) | 被引量 : 0次 | 上传用户：liongliong571

【摘要】

：

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of

【作者】

：

Chin-Hsin Lin Marek Syrzycki

【机构】

：

不详

【出处】

：

电路与系统(英文)

【发表日期】

：

2011年4期

【关键词】

：

Vernier Time-to-Digital CONVERTER Dynamic-Logic PHASE FREQUENCY DETECTOR Vernier

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This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution.

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Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

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