为解决如何以低面积开销为系统芯片(SoC)构建透明路径测试访问机制从而有效进行测试复用的问题,提出了SoC级透明路径构建方法,将透明路径构建问题转化为0-1规划问题,同时考虑测试调度,以缩短测试加载时间和减小面积开销为优化目标,利用IP模块内部的透明路径和模块间互连关系为每个待测模块构建测试访问通路。实验结果表明:该透明路径构建方法的面积开销比Ghosh方法降低50%,测试加载时间比Yoneda方法大大缩短,验证了该方法的有效性。 To solve the problem of how to construct a transparent path test access mechanism for system chip (SoC) with low area overhead so as to effectively test and reuse, a soC-level transparent path construction method is proposed, which transforms the transparent path construction problem into a 0-1 programming problem, At the same time, the test scheduling is considered. In order to shorten the test load time and reduce the area overhead, the test access path is constructed for each module under test by using the transparent path inside the IP module and the inter-module interconnection. The experimental results show that the area cost of the method for constructing a transparent path is reduced by 50% compared with that of the Ghosh method, and the test loading time is greatly shortened compared with the Yoneda method, which proves the effectiveness of the method.