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本文提出了一种新型低功耗D锁存器,通过在直接交叉耦合D锁存器的接地端串联一个由输出反馈控制的NMOS管,部分消除了锁存器状态转换过程中的竞争现象,从而减小了电路的短路功耗,在数据保持阶段由晶体管的堆叠效应降低了电路的漏功耗。标准电源电压下HSPICE仿真测试结果表明,与直接交叉耦合D锁存器相比,新型D锁存器的漏功耗与动态功耗分别下降了13.5%和61.9%;与传输门D锁存器相比,漏功耗与动态功耗分别下降了9.3%和2.1%。应用新型D锁存器实现了4位伪随机序列信号发生器,仿真结果表明电路具有正确的逻辑功能,与传输门D锁存器构成的伪随机序列信号发生器相比动态功耗降低了18.9%,漏功耗降低了16.7%。
In this paper, a new type of low-power D-latch is proposed. By partially connecting an NMOSFET controlled by output feedback at the ground of the D-latch, the competitive phenomenon in the latch-state transition is partially eliminated. Thereby reducing the circuit short-circuit power consumption, reducing the circuit’s drain power dissipation during the data hold phase by the stacking effect of the transistors. The results of HSPICE simulation under standard power supply voltage show that the drain power and dynamic power of the new D-type latch drop by 13.5% and 61.9% respectively compared with the direct cross-coupling D-type latch. Compared with the D-latch Compared with leakage power and dynamic power consumption decreased by 9.3% and 2.1%. The new D-latch realizes a 4-bit pseudo-random sequence signal generator. The simulation results show that the circuit has the correct logic function, and the dynamic power consumption is reduced by 18.9 compared with the pseudo-random sequence signal generator formed by the D-latch of the transmission gate %, Leakage power consumption decreased by 16.7%.