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针对雷达系统小型化和低功耗的应用需求,提出一种宽带雷达数字接收机中数字下变频器的设计方法。通过采用系统采样频率等于输入信号中心频率4倍的采样技术,结合混频器的特殊实现结构以及半带FIR滤波器抽头系数的特点,经过详细的理论推导后,给出该方法具体的硬件实现结构,能够显著降低数字下变频信号处理的复杂程度,有效减少对硬件逻辑资源,尤其是硬件乘法器的消耗。该方法在FPGA中实现时,与使用传统方法设计的数字下变频器相比,硬件逻辑资源消耗减少83.65%,功耗降低约110 mW。最后,设计实例结果验证了设计方法的正确性以及很好的工程实用性。
Aiming at the demand of miniaturization and low power consumption of radar system, a design method of digital down converter in wideband radar digital receiver is proposed. By adopting the sampling technique that the system sampling frequency is equal to 4 times the center frequency of the input signal and the characteristics of the mixer’s special implementation structure and the half-band FIR filter tap coefficients, the detailed hardware implementation of this method is given after detailed theoretical derivation Structure, can significantly reduce the complexity of digital down-conversion signal processing, effectively reducing the consumption of hardware logic resources, especially hardware multipliers. When implemented in an FPGA, the method reduces hardware logic resource consumption by 83.65% and reduces power consumption by approximately 110 mW compared to a digital downconverter designed using conventional methods. Finally, the design example results verify the correctness of the design method and good engineering practicability.