基于CMOS工艺的单光子雪崩二极管的盖革模式仿真

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采用互补金属氧化物半导体(CMOS)工艺和p阱保护环,使用SILVACO公司的ATLAS软件进行器件结构设计和仿真,得到了能正常工作在盖革模式下的单光子雪崩二极管(SPAD)。仿真结果表明:设计的器件结构中p+/n-阱结降低了结附近的电场强度,并且低于平面pn结的电场强度,从而起到了抑制二极管发生边缘击穿的保护作用;电场强度和碰撞产生率呈正相关,并得出了电子、空穴的雪崩产生率与纵向位置的关系曲线及器件中某一个点处的电子雪崩产生率和偏置电压的关系曲线。仿真结果对基于CMOS工艺的SAPD结构设计具有一定的指导意义。 The structure of the device was simulated and simulated by SILVACO ATLAS software using complementary metal-oxide-semiconductor (CMOS) process and p-well guard ring. The single-photon avalanche diode (SPAD) was successfully fabricated in Geiger mode. The simulation results show that the p + / n-well junction in the designed device structure reduces the electric field strength near the junction and is lower than the electric field strength of the plane pn junction, thus protecting the diode from edge breakdown. The electric field intensity and the collision And the relationship between the avalanche generation rate of electron and hole and the vertical position and the relationship between the generation rate of electron avalanche and the bias voltage at a certain point in the device are obtained. The simulation results have certain guiding significance for the SAPD structure design based on CMOS technology.
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