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介绍了利用复杂的可编程逻辑器件 (CPL D)和双端口 RAM设计 VXI总线接口的方法 ,它适用于寄存器基的 VXI总线模块。这种设计已在科研实际应用中取得成功 ,因此 ,对于从事 VXI总线计算机自动测控系统工作的科研人员有一定的参考价值。
A method of designing a VXI bus interface using complex programmable logic device (CPL D) and dual port RAM is presented, which is suitable for register-based VXI bus modules. This design has been successful in the practical application of scientific research, therefore, for the VXI bus computer automatic measurement and control system researchers have some reference value.