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时间数字转换器(Time-to-Digital Converter,TDC)是全数字锁相环(All-Digital PhaseLocked Loop,ADPLL)中的一个重要模块,其功耗也是ADPLL系统总功耗的主要部分。针对伪差分反相器链结构的TDC,提出了一种功能不受亚稳态影响的基于D触发器链的TDC使能电路,并对TDC的结构进行改进,以降低TDC系统的功耗。采用SMIC 0.18μm CMOS工艺对电路进行设计和仿真,仿真结果表明,TDC系统的功耗可以降低74%以上。
Time-to-Digital Converter (TDC) is an important module in the All-Digital PhaseLocked Loop (ADPLL). Its power consumption is also a major part of the total power consumption of an ADPLL system. For the TDC of pseudo-differential inverter chain structure, a TDC-enabled circuit based on D-flip-flop chain whose function is not affected by metastability is proposed, and the structure of TDC is improved to reduce the power consumption of TDC system. The SMIC 0.18μm CMOS process is used to design and simulate the circuit. The simulation results show that the power consumption of TDC system can be reduced by more than 74%.