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采用标准0.18 μm CMOS工艺,设计了一种可编程分频器.基于基本分频单元的特殊结构,对除2/除3单元级联式可编程分频器的关键模块进行改进,将普通的CML型锁存器集成为包含与门的锁存器,提高了电路的集成度,有效地降低了电路功耗,提升了整体电路速度,并使版图更为紧凑.后仿真结果表明,在1.8V电源电压,输入频率fin=1 GHz的情况下,可实现任意数且步长为1的分频比,相位噪声为-173.1 dBc/Hz@1 MHz,电路功耗仅为9 mW.“,”A programmable frequency divider was proposed in a 0.18 μm standard CMOS.Based on the special structure of basic dividing cell,the 2/3 dividing cell was improved,which was the key module of the cascaded programmable frequency divider.The ordinary CML D-latch was integrated into AND_latch,thus increasing the chip integration,effectively reducing the power consumption of the circuit,raising the overall circuit speed,and tightening the layout more compact.The post-simulation results showed that from a supply voltage of 1.8 V and an input frequency of 1 GHz,arbitrary integer frequency ratio was available.The circuit had a phase noise of-173.1 dBc/Hz@1 MHz and a power consumption of 9 mW.