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提出了一种应用于低电源电压的改进型高速超低功耗双电流动态锁存比较器。在不增加电路复杂度的情况下,通过在传统双电流动态比较器中增加一条额外的放电途径,使得比较器能够快速地从复位状态进入到再生阶段,缩短了整个过程的延迟时间,更重要的是扩宽了输入共模范围,同时降低了延迟时间对共模输入电压的依赖性。电路基于SMIC 0.18μm CMOS工艺进行设计与仿真,仿真结果表明,在时钟频率为1GHz,输入电压差为5mV时,延迟时间为294ps,功耗仅为52μW。
An improved high speed and ultra low power consumption dual current dynamic latch comparator for low power supply voltage is proposed. Without increasing the circuit complexity, by adding an extra discharge path to the conventional two-current dynamic comparator, the comparator can quickly move from the reset state to the regeneration phase, which shortens the delay time of the whole process and more importantly Is to broaden the input common-mode range, while reducing the delay time on the common-mode input voltage dependence. The circuit is designed and simulated based on the SMIC 0.18μm CMOS process. The simulation results show that the delay time is 294ps and the power consumption is only 52μW when the clock frequency is 1GHz and the input voltage difference is 5mV.