通常在计算机系统中,上升时间少于1ns时,集成电路(IC)的封装结构就成为信号变差和噪声余量减少的主要因素。设计人员必须在早期的设计过程中通过模拟,预测系统的性能,以便及时地把高质量的产品投向市场。 不断增加的系统复杂性,更高的集成度和更快的时钟速率,这些都有助于改善系统的性能。但其中的每一项都会影响到设计封装工艺以及系统的设计过程。时钟速率越快意味着定时余量越小,使转 Often, in a computer system, the IC packaging structure is a major factor in signal degradation and noise margin reduction when the rise time is less than 1 ns. Designers must simulate and predict system performance early in the design process to bring high-quality products to market in a timely manner. Increasing system complexity, higher integration, and faster clock speeds help improve system performance. But each one of them will affect the design of packaging technology and system design process. The faster the clock rate means the smaller the timing margin, so turn