结构和电路设计是 CMOS 超大规模集成电路的两种最有效的功率减小方法。数学运算被应用于构造快速傅里叶变换(FFT)功率有效结构中。该结构采用异步电路技术,与其它 FFT 结构相比能明显降低功率。本文提出了一种比传统设计方法更明显降低功率的多速率信号处理技术和异步设计方式的算法;构造了一种完成该设计一部分的测试芯片,并做了功率比较。参6 Structure and circuit design are the two most efficient power reduction methods for CMOS VLSI. Mathematical operations are applied to construct Fast Fourier Transform (FFT) power efficient structures. The structure of asynchronous circuit technology, compared with other FFT structure can significantly reduce the power. In this paper, an algorithm of multi-rate signal processing and asynchronous design with more obvious power reduction than traditional design methods is proposed. A test chip that completes part of the design is constructed and the power comparison is made. Participation 6