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本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断ΣΔ调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18μm,1.8VSM IC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15μs的锁定时间.
In this paper, a 1.9GHz fractional / integer-phase locked loop frequency synthesizer with self-tuning and self-adaptive function is proposed. The frequency synthesizer uses a combination of analog and digital tuning to improve phase noise performance. Used to achieve automatic bandwidth adjustment, you can shorten the cycle of the establishment of the loop by turning on or off the ΣΔ modulator output to achieve fractional and integer frequency divider two modes of operation, with only one programmable counter pulse swallow pulse divider Function. Using bias filter technology and differential inductance, the VCO has very low phase noise; the VCO can operate in the 1.7GHz to 2.1GHz tuning range by using a switched capacitor array. The frequency synthesis Implemented in a 0.18μm, 1.8VSM IC CMOS process, the SpectreVerilog simulation shows that the frequency synthesizer has a loop bandwidth of approximately 100kHz and better phase noise than -123dBc / Hz at 600kHz with lock-in times less than 15μs.