论文部分内容阅读
提出了一种适于实现数据通路(Datapath)逻辑的FPGA结构FDP。该结构的主要创新之处在于采用了两条通用反馈逻辑、基于全加器的通用逻辑单元、基于信号流的不对称连线结构和并行的测试扫描链。SPICE模拟结果表明,用0.8μm的工艺,FDP块内延时2.7ns,平均进位链延时0.1ns。工艺映射的实验结果显示,在实现数据通路中的常用电路时,新模块比基于LUT的FPGA模块平均节省70%的MOS管数
An FPGA fabric FDP suitable for implementing data path (Datapath) logic is proposed. The main innovation of this structure lies in adopting two common feedback logic, universal logic unit based on full adder, asymmetrical connection structure based on signal flow and parallel test scan chains. SPICE simulation results show that, with 0.8μm process, FDP block delay 2.7ns, the average carry chain delay 0.1ns. The experimental results of the process map show that the new module saves an average of 70% of the MOS tube count over the LUT based FPGA module when implementing commonly used circuits in the data path