针对IEEE802.11a协议物理层高速卷积码解码器最高54M速率的需求,设计了高速Viterbi译码器。首先提出一种新型基四的Viterbi译码算法,采用大量存储器代替运算逻辑单元,提高速度;同时对回溯算法也作了改进,使用IP核双口RAM完成高速回溯。接着通过算法仿真完成算法的验证,采用优化的硬件实现方案,以64路全并行结构完成了高速基四算法的Viterbi译码器的设计,并将该设计应用到实际工程中。 Aiming at the demand of IEEE802.11a high-speed convolutional code decoder at physical layer up to 54M, a high-speed Viterbi decoder is designed. First of all, a new type of Viterbi decoding algorithm based on quadruplex is proposed, which uses a large amount of memory to replace the arithmetic logic unit to improve the speed. At the same time, the backtracking algorithm is also improved. Then, the algorithm is verified by the algorithm simulation, and the optimized hardware implementation is adopted. The design of the Viterbi decoder with high-speed base four algorithm is completed with 64 full-parallel structures, and the design is applied to the actual project.