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由于三维集成电路是集成电路发展的一个主要趋势,片上网络已经被讨论用于解决大规模三维集成电路的互连问题。在三维片上网络中,拓扑结构的选择至关重要。该文通过数学分析和软件仿真,对片上网络的两种常见拓扑结构(torus结构和mesh结构)在三维片上网络中的通信性能(传输延时和吞吐量)和面积开销进行了评估。结果表明:在向片上网络中注入的数据包流量均匀分布的情况下,采用维序路由时,三维torus结构比三维mesh结构具有更优的吞吐量和延时性能,但需要更多的面积开销。
As three-dimensional integrated circuits are a major trend in the development of integrated circuits, on-chip networks have been discussed to solve the interconnection problems of large-scale three-dimensional integrated circuits. In 3D on-chip network, the choice of topology is crucial. Through mathematical analysis and software simulation, this paper evaluates the communication performance (transmission delay and throughput) and area overhead of two common topologies (the torus structure and mesh structure) of the on-chip network in the three-dimensional chip network. The results show that the three-dimensional torus structure has better throughput and delay performance than the three-dimensional mesh structure when the traffic is injected evenly into the on-chip network, but more area overhead is needed .