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在高速逻辑设计中，需要考虑避免出现振铃、串扰等传输线现象。就此详细讨论了在Ultra2SCSI单端和差分两种模式兼容下，其PCB的输出阻抗与连接电缆的两种阻抗的匹配问题，并介绍了在这样的高速逻辑系统中，PCB设计通常要考虑的一些其它问题。
In high-speed logic design, need to consider to avoid ringing, crosstalk and other transmission line phenomenon. This paper discusses in detail the matching between the output impedance of PCB and the two impedances of the connecting cable under the compatibility of Ultra2SCSI single-ended and differential modes, and introduces some common considerations of PCB design in such a high-speed logic system other questions.