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基于IBM 0.18μm SOI CMOS工艺,设计了一款用于WLAN的高效率CMOS功率放大器。为了提高电路的可靠性,该放大器的驱动级和输出级均采用自适应偏置电路,使得共栅管和共源管的漏源电压分布更为均衡。该芯片采用两级共源共栅结构,片内集成了输入匹配电路和级间匹配电路。测试结果表明,该放大器的增益为23.9dB,1dB压缩点为23.9dBm,效率为39.4%。当测试信号为IEEE 802.11g 54 Mb/s,在EVM为3%处,输出功率达到16.3dBm。
Based on the IBM 0.18μm SOI CMOS process, a high efficiency CMOS power amplifier for WLANs is designed. In order to improve the reliability of the circuit, both the driver stage and the output stage of the amplifier adopt an adaptive bias circuit to make the drain-source voltage distribution of the cascode and the common source more balanced. The chip uses a two-level cascode structure, the chip integrates the input matching circuit and the stage matching circuit. The test results show that the amplifier gain of 23.9dB, 1dB compression point of 23.9dBm, the efficiency of 39.4%. When the test signal is IEEE 802.11g 54 Mb / s, the output power reaches 16.3 dBm at 3% of the EVM.