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介绍了12 bit,10 MS/s流水线结构的模数转换器IP核设计。为了实现低功耗,在采样电容和运放逐级缩减的基础上,电路设计中还采用了没有传统前端采样保持放大器的第一级流水线结构,并且采用了运放共享技术。瞬态噪声的仿真结果表明,在10 MHz采样率和295 kHz输入信号频率下,由该方法设计的ADC可以达到92.56 dB的无杂散动态范围,72.97 dB的信号噪声失调比,相当于11.83个有效位数,并且在5 V供电电压下的功耗仅为44.5 mW。
The design of analog-to-digital converter IP core with 12 bit and 10 MS / s pipeline structure is introduced. In order to achieve low power consumption, the sampling capacitor and operational amplifier step by step based on the reduction, the circuit design also uses a traditional front-end sample and hold amplifier first-stage pipeline architecture, and uses op amp sharing technology. The simulation results of transient noise show that the ADC designed by this method achieves 92.56 dB of spurious-free dynamic range and 72.97 dB of signal noise mismatch, which is equivalent to 11.83 at 10 MHz sampling rate and 295 kHz input signal frequency Effective number of bits, and consumes only 44.5 mW at 5 V supply.