在约翰逊计数分频器的基础上,设计了一款双级结构分频器,采用系数自适应分配技术,显著提升了分频器的工作频率,并有效降低功耗。基于45nm CMOS工艺进行仿真,结果表明:该分频器最高工作频率可达8GHz,在1GHz时,49分频的双级可编程分频器功耗仅为63μW,在8GHz时,功耗为312μW。与典型的约翰逊结构相比,双级分频器工作频率可提升1.6倍,在分频器系数设置为6时,最大功耗优化比达到51.82%。 Based on the Johnson counter divider, a two-stage structure frequency divider is designed, which adopts the adaptive allocation of coefficients to significantly improve the working frequency of the divider and reduce the power consumption effectively. Based on the 45nm CMOS process simulation results show that: the maximum operating frequency of the divider up to 8GHz at 49GHz frequency divider 49 programmable two-stage programmable power amplifier consumes only 63μW at 8GHz, the power consumption of 312μW . Compared with the typical Johnson structure, the operating frequency of the two-stage frequency divider can be increased by 1.6 times. When the divider coefficient is set to 6, the maximum power consumption optimization ratio reaches 51.82%.