论文部分内容阅读
当前芯片里的电路与系统日趋复杂,超大规模集成电路(VLSI)设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平/垂直约束图提取版图中各单元的坐标,并利用李氏算法查找出最佳布线路径。
The current circuits and systems in the chip are becoming increasingly complex, VLSI design technology is also gradually increasing. VLSI design generally adopts the method of hierarchical design. The layout design process is one of the most critical steps in the overall VLSI grading design. Single-Sequence based on the integrated circuit layout is the application of SS codec in the chip placement of each unit to optimize chip area utilization to achieve maximum. This paper focuses on the design of the connections between the cells after the SS sequence is generated and how to extract the coordinates of each cell in the layout according to the horizontal / vertical constrained graph, and finds out the optimal routing path by using the Lee algorithm.