为了制作高速、高密度CMOS VLSI 电路,必须减小器件尺寸.但是,由于(?)沟道和p 沟道器件之间间距的限制,即若其间距太小,则会直接影响抗闩锁能力,并使器件的隔离性能变差.因而,如何减小其间距,且使其性能不受影响是目前人们所关注的问题.采用深隔离U 形槽技术为此提供了一条解决的途径,它不仅能大大减小n-p 间距,且能提高抗闩锁能力,还可控广用于双极器件中.深隔离U 形槽技术的工艺步骤大致是:先生长一层薄 In order to fabricate high-speed, high-density CMOS VLSI circuits, the device size must be reduced, however, due to the limited spacing between (?) And p-channel devices, , And make the device’s isolation performance worse.Therefore, how to reduce its spacing, and to make its performance is not affected by the current concern.Using deep isolation U-groove technology provides a solution to this Not only can greatly reduce the np spacing, and can improve the anti-latch-up capability, but also widely used in bipolar devices. Deep isolation U-groove technology process steps roughly: first, a thin layer