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基于0.18μm CMOS工艺,设计了一种改进的2位全并行A/D转换器。ADC的输入信号采用差分输入形式,差模输入信号经过源跟随器后直接进入比较器,去除了参考电压所需的电阻网络和模拟采样保持电路模块。在编码电路之后加入一个数字采样保持器,实现了时钟对量化信号的采集和数据同步对齐。仿真结果表明,在1.8V工作电压、25μA和15μA偏置电流下,可以对频率为4 MHz,摆幅为100mV的两路差模信号进行量化,整体功耗小于0.5mW。
Based on the 0.18μm CMOS process, an improved 2-bit full-parallel A / D converter is designed. The input signal of ADC adopts the form of differential input, the differential mode input signal enters the comparator directly through the source follower, has removed the resistance network and analog sample-hold circuit module required for the reference voltage. A digital sample-and-hold is added after the encoding circuit to allow the clock to acquire and synchronize the quantized signals. The simulation results show that at 1.8V operating voltage, 25μA and 15μA bias current, the two differential mode signals with frequency of 4 MHz and swing amplitude of 100mV can be quantized, and the overall power consumption is less than 0.5mW.