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NIOS Ⅱ是Altera公司推出的第二代IP软核处理器,它与其他IP核构成了SOPC系统的主要部分。用户可以通过自定义逻辑的方法在SOPC设计中添加自己开发的IP核,使设计简单高效。本文利用FPGA中内嵌的NIOS Ⅱ处理器设计了一种数据采集系统。通过FPGA内部自带的双口RAMIP核和乒乓操作,实现数据的缓存。利用NIOS Ⅱ嵌入式软核实现缓存数据的读取、存储和传输。缓存数据的读取采用自定义组件的方式实现。该系统避免了控制单元与时序单元的分立设计,简化了电路,增强了可靠性,具有较好的可移植性。经试验验证,该系统能够较好地实现数据的采集,运行效果良好。
NIOS II is Altera’s second-generation IP soft-core processor, which forms a major part of the SOPC system with other IP cores. Users can add their own developed IP cores to the SOPC design through the method of custom logic, which makes the design simple and efficient. In this paper, FPGA embedded NIOS Ⅱ processor designed a data acquisition system. Through the FPGA’s internal dual-port RAMIP core and ping-pong operation, data cache. Use NIOS Ⅱ embedded soft core to realize the reading, storing and transmitting of cached data. Cache data read using custom components to achieve. The system avoids the separate design of the control unit and the timing unit, simplifies the circuit, enhances the reliability and has better portability. The experimental verification, the system can achieve better data collection, running well.