文中分析高速背板设计中所面临的问题,给出相应的设计准则。在此基础上,以所设计的交换机背板为例给出利用时钟缓冲分配芯片实现的时钟信号分配电路的实例。最后,说明针对时钟电路的设计所采取的具体措施。结果表明,利用上述设计方案可以使整个系统在90MHz的时钟频率下稳定工作,实现高达2·88Gbps的数据传输速率。 The paper analyzes the problems faced in the design of high-speed backplane, and gives the corresponding design criteria. On this basis, an example of the clock signal distribution circuit realized by using the clock buffer distribution chip is given by taking the switch backplane as an example. Finally, explain the design of the clock circuit for the specific measures taken. The results show that using the above design scheme can make the whole system work stably at a clock frequency of 90MHz and achieve a data transmission rate of up to 2.88Gbps.