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在很多应用场合,静态随机存贮器(RAM)需要一个超低功率的备用状态,因为这样大的存贮系统就可以由适当大小的电池组长时间保持。这个要求已迫使把许多系统用相对昂贵的CMOS RAM来设计,以满足很低的电流(氵曵)漏需要(每一存贮单元小于10nA)。以前关于NMOS RAM的电池备用的努力曾要求在降低的V_(cc)下运行。它仅部分地减少功率,或者为存贮阵列另加分开的供电引线,它要增加元件的引线总数。
In many applications, static random access memory (RAM) requires an ultra-low power standby because such a large storage system can be held by a properly sized battery pack for a long time. This requirement has forced many systems to be designed with relatively expensive CMOS RAM to meet the very low current drain requirement (less than 10 nA per memory cell). Previous efforts on battery backup for NMOS RAM have required operation at reduced V_ (cc). It only partially reduces power, or it provides additional separate supply leads for the memory array, which increases the total number of leads for the component.