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随着现场可编程门阵列(FPGA)的出现,基于软件无线电的数字中频技术目前被广泛地应用到3G基站中。结合多速率信号处理理论,采用分级实现的方法对码分多址扩频复用(WCDMA)基站中的数字中频接收系统进行优化设计,提出一种基于FPGA硬件的IP核实现方案。仿真结果表明,IP核简洁的图形化界面保证设计可靠性的同时优化了硬件资源的配置,极大地减少了计算量进而显著缩短了设计时间。
With the advent of field programmable gate arrays (FPGAs), digital radio technologies based on software-defined radio are now widely used in 3G base stations. Combining with the theory of multi-rate signal processing, the method of hierarchical implementation is used to optimize the design of digital IF receiving system in CDMA (Code Division Multiple Access) Spread Spectrum Multiplexing (WCDMA) base station. An IP core implementation scheme based on FPGA hardware is proposed. The simulation results show that the simple graphical interface of IP core ensures the reliability of design and optimizes the configuration of hardware resources, which greatly reduces the computational cost and shortens the design time significantly.