本文介绍了一种采用先进流水技术的模糊控制器(FMC)的VLSI结构.该结构的运算采用了单指令流多数据流(SIMD)方式.以及多种先进的流水技术,包括:细分流水、流水的集中式动态调度、超级标量流水等.通过这些技术处理,使每条模糊运算指令平均所需时钟周期数(CPI)=05.基于硬件描述语言(VHDL)的模拟和综合结果表明,采用15μmCMOS工艺库,电路的规模约为20k单元面积(内含2kRAM).在最坏情况下,最高时钟频率可达30MHz,平均每秒处理模糊规则数(FLIPS)=60M. This paper presents a VLSI architecture of a fuzzy controller (FMC) using advanced pipeline technology that uses a SIMD (Single Instruction Flow Multiple Data) approach and a number of advanced pipeline techniques including: , Centralized dynamic scheduling of pipeline, superscalar pipeline, etc. By these techniques, the average required number of clock cycles (CPI) per fuzzy instruction is 5. Based on the hardware description language (VHDL) simulation and synthesis results show that, 15μmCMOS technology library, the circuit size is about 20k unit area (containing 2kRAM). In the worst case, the highest clock frequency up to 30MHz, the average number of fuzzy rules per second processing (FLIPS) = 60M.