A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer. A new low leakage 3 × VDD-tolerant electrostatic discharge (ESD) detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process. NMOS transistor operates in high voltage range and it is unnecessary to use any deep N-well. The proposed detection circuit can generate a mA current to turn on the substrate triggered silicon-controlled rectifier (STSCR) Under the ESD stress. Normal operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 88 nA under 3 × VDD bias at 25 ° C. The simulation result shows the circuit can be successfully used for 3 × VDD-tolerant I / O buffer.