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首次提出一种新的具有双面界面电荷岛结构的SOI高压器件(DCI SOI)。该结构在SOI器件介质层上下界面分别注入形成一系列等距的高浓度n+区及p+区。器件外加高压时,纵向电场所形成的反型电荷将被未耗尽n+区内高浓度的电离施主束缚在介质层上界面,同时在下界面积累感应电子。引入的界面电荷对介质层电场(EI)产生附加增强场(ΔEI),使介质层承受更高耐压,同时对顶层硅电场(ES)产生附加削弱场(ΔES),避免在硅层提前击穿,从而有效提高器件的击穿电压(BV)。详细研究DCI SOI工作机理及相关结构参数对击穿电压的影响,在5μm介质层、1μm顶层硅上仿真获得750 V高耐压,较常规结构提高254.4%,其中,附加场ΔEI和ΔES分别达到642.5 V/μm和24 V/μm。
For the first time, a new SOI high voltage device (DCI SOI) with a double-sided interface charge island structure is proposed. The structure is injected into the upper and lower interfaces of the SOI device dielectric layer respectively to form a series of equidistant high-concentration n + and p + regions. When the device is subjected to a high voltage, the charge of the opposite type formed by the longitudinal electric field will be bound to the upper interface of the dielectric layer by the ionized donor of high concentration in the non-depleted n + region, while the accumulated charge induces electrons at the lower interface. The introduced interfacial charge generates an additional enhanced field (EIi) for the dielectric layer electric field (EI), exposing the dielectric layer to higher withstand voltages and creating an additional field of weakening (ES) on the top silicon electric field (ES) Wear, thereby effectively increasing the breakdown voltage of the device (BV). The effects of DCI working mechanism and related structural parameters on the breakdown voltage were studied in detail. The high breakdown voltage of 750 V was obtained at 5μm dielectric layer and 1μm top layer silicon, which was 254.4% higher than that of the conventional structure. In addition, ΔEI and ΔES of additional field reached 642.5 V / μm and 24 V / μm.