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提出了多电压时间限制下电路功耗最小的高层综合设计算法 ,其输入为数据流图及时间限制条件 .由于多电压设计会引起低层布局时的连线复杂性提高 ,所以提出的算法在进行高层调度过程同时考虑了低层分区问题 ,即算法利用调度步骤降低功耗 ,利用分区步骤来减小连线的复杂性 .该算法的时间复杂性为O(n2 ) ,n是DFG图中的结点个数 .大量的DSP基准实验表明该算法使得电路功耗平均降低 4 6 5 % .
A high-level synthesis design algorithm with the lowest power consumption under multi-voltage time-limit is proposed, and its input is data flow graph and time limit condition.As the multi-voltage design will cause the connection complexity when low-level layout increases, the proposed algorithm is underway The high-level scheduling process considers the low-level partitioning problem at the same time, that is, the algorithm uses scheduling steps to reduce power consumption and the partitioning steps to reduce the complexity of the connection. The time complexity of the algorithm is O (n2), n is the node in DFG graph A large number of DSP benchmark experiments show that the algorithm reduces the average power consumption of the circuit by 465%.