Scan-based testing methodologies remedy the testability problem of sequential circuits;yet they suffer from prolonged test time and excessive test power due to numerous shift operations.The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test.data in the scan chain for the generation of the subsequent test stimulus,thus reducing both test time and test data volume.We propose a pair of scan approaches in this paper;in the first approach,a test stimulus partially consists of the preceding stimulus,while in the second approach,a test stimulus partially consists of the preceding test response bits.Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data,thus decreasing scan chain transitions during shift operations.The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms,boosting test time reductions.The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits. Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test.data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. B.oth proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulatio nulations which include test stimuli ordering and partitioning algorithms, boosting test time reductions. the experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS 89 benchmark circuits.