设计了一种用于过零脉宽检测QPSK全数字解调器的同步电路,利用动态增减计数脉冲同步法实现了其功能,避免了相干检测QPSK全数字同步电路中的复杂电路,如锁相环,乘法器等的使用。该电路采用FPGA器件为硬件载体,借助VHDL语言实现其主要功能,原理清晰,易于实现,稳定可靠,性价比高,真正实现了QPSK的全数字同步,具有较高的使用价值和市场潜力。 A synchronous circuit for zero-crossing pulse width detection (QPSK) full digital demodulator is designed. It realizes its function by using the dynamic up-down counting pulse synchronization method and avoids the coherent detection of complex circuits in the QPSK all-digital synchronous circuit such as lock Phase-loop, multiplier, etc. use. The circuit uses FPGA device as hardware carrier, and achieves its main function by means of VHDL language. The principle is clear, easy to implement, stable and reliable, and cost-effective. It realizes the all-digital synchronization of QPSK and has high use value and market potential.